Computer Architecture for JNTU-H 18 Course (III - I - EEE/Prof. Elec.-I - EE511PE) (Decode)

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UNIT - I: Introduction to Computer Organization Architecture and function of general computer system, CISC Vs RISC, Data types, Integer Arithmetic - Multiplication, Division, Fixed and Floating-point representation and arithmetic, Control unit operation, Hardware implementation of CPU with Micro instruction, microprogramming, System buses, Multi-bus organization. (Chapter - 1) UNIT - II: Memory Organization System memory, Cache memory - types and organization, Virtual memory and its implementation, Memory management unit, Magnetic Hard disks, Optical Disks. Input – Output Organization Accessing I/O devices, Direct Memory Access and DMA controller, Interrupts and Interrupt Controllers, Arbitration, Multilevel Bus Architecture, Interface circuits - Parallel and serial port. Features of PCI and PCI Express bus. (Chapters - 2, 3) UNIT - III: 16 AND 32 Microprocessors 80x86 Architecture, IA – 32 and IA – 64, Programming model, Concurrent operation of EU and BIU, Real mode addressing, Segmentation, addressing modes of 80x86, Instruction set of 80x86, I/O addressing in 80x86. (Chapter - 4) UNIT - IV: Pipelining Introduction to pipelining, Instruction level pipelining (ILP), compiler techniques for ILP,Data hazards, Dynamic scheduling, Dependability, Branch cost, Branch Prediction, Influence on instruction set. (Chapter - 5) UNIT - V: Different Architectures VLIW Architecture, DSP Architecture, SoC architecture, MIPS Processor and programming. (Chapter - 6)

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Author: [A. P. Godse, Dr. D.A. Godse] Pages: 172 Edition: 2021 Vendors: Technical Publications