VLSI Design for Anna University R17 CBCS (VI- ECE & VII-EEE/Prof. Elec.-IV - EC8095)

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UNIT - I Introduction to MOS Transistor MOS Transistor, CMOS logic, Inverter, Pass Transistor, Transmission gate, Layout Design Rules, Gate Layouts, Stick Diagrams, Long-Channel I-V Charteristics, C-V Charteristics, Non ideal I-V Effects, DC Transfer characteristics, RC Delay Model, Elmore Delay, Linear Delay Model, Logical effort, Parasitic Delay, Delay in Logic Gate, Scaling. UNIT - II Combinational MOS Logic Circuits Circuit Families : Static CMOS, Ratioed Circuits, Cascode Voltage Switch Logic, Dynamic Circuits, Pass Transistor Logic, Transmission Gates, Domino, Dual Rail Domino, CPL, DCVSPG, DPL, Circuit Pitfalls. Power : Dynamic Power, Static Power, Low Power Architecture. UNIT - III Sequential Circuit Design Static latches and Registers, Dynamic latches and Registers, Pulse Registers, Sense Amplifier Based Register, Pipelining, Schmitt Trigger, Monostable Sequential Circuits, Astable Sequential Circuits. Timing Issues : Timing Classification of Digital System, Synchronous Design. UNIT - IV Design of Arithmetic Building Blocks and Subsystem Arithmetic Building Blocks : Data Paths, Adders, Multipliers, Shifters, ALUs, power and speed tradeoffs, Case Study : Design as a tradeoff. Designing Memory and Array Structures : Memory Architectures and Building Blocks, Memory Core, Memory Peripheral Circuitry. UNIT - V Implementation Strategies and Testing FPGA Building Block Architectures, FPGA Interconnect Routing Procedures. Design for Testability : Ad Hoc Testing, Scan Design, BIST, IDDQ Testing, Design for Manufacturability, Boundary Scan.

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Pages: 316 Edition: 2022 Vendors: Technical Publications