Syllabus VLSI Testing and Design for Testability - (CEC362) UNIT I TEST REQUIREMENTS AND METRICS Validation platforms - SOC design methodology, IP components, Integration, Clocking, I/Os and interfaces, Device modes, Logic, memories, analog, I/Os, power management; Test requirements-Test handoffs, Testers Where DUT and DFT fit into design / framework; Test - ATPG, DFT, BIST, COF, TTR; Test cost metrics and test economics; Logic fault models - SAF, TDF, PDF, Iddq, St-BDG, Dy-BDG, SDD; Basics of test generation and fault simulation- Combinational circuits, Sequential; Specific algorithmic approaches, CAD framework, Optimisations. (Chapter - 1) UNIT II SCAN DESIGN AND BIST Scan Design - Scan design requirements, Types of scan and control mechanisms, Test pattern construction for scan, Managing scan in IPs and SOCs, Scan design optimisations, Partitioning, Clocking requirements for scan and delay fault testing, Speed of operation; BIST - Framework, Controller configurations, FSMs, LFSRs, STUMPS architecture, Scan compression and bounds, Test per cycle, Test per scan, Self-testing and self-checking circuits, Online test. (Chapter - 2) UNIT III MEMORY TEST AND TEST INTERFACES Memory Test - Memory fault models, Functional architecture as applicable to test, Test of memories, Test of logic around memories, BIST controller configuration, Test of logic around memories, DFT and architecture enhancements, Algorithmic optimisations; Test Interfaces-Test control requirements, Test interfaces - 1500, JTAG, Hierarchical, serial control, Module / IP test, SOC test, Board test, System test, Boundary scan. (Chapter - 3) UNIT IV DESIGN CONSIDERATIONS AND POWER MANAGEMENT DURING TEST Design Considerations- Design considerations, Physical design congestion, Partitioning, Clocks, Test modes, Pins, Test scheduling, Embedded test, Architecture improvements, Test in the presence of security; Power management during test - Methods for low power test, ATPG methods, DFT methods, Scan methods, Low power compression, Test of power management, Implications of power excursions, Optimisations. (Chapter - 4) UNIT V ANALOG TEST Test requirements. DFT methods. BIST methods. Test versus measurement. Defect tests versus performance tests. Tests for specific modules - PLL, I/Os, ADC, DAC, SerDes, etc. RF test requirements. (Chapter - 5)
