VLSI and Chip Design for BE Anna University R21CBCS (V - ECE - EC3552 & Sem-VII/VIII/Open Electie IV - CSE/IT/EEE/AI&DS/CS&BS/CSE(AI&ML)/Mech./Civil - OEC353)

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Syllabus VLSI and Chip Design - [EC3552] UNIT I MOS TRANSISTOR PRINCIPLES MOS logic families (NMOS and CMOS), Ideal and Non Ideal IV Characteristics, CMOS devices. MOS(FET) Transistor Characteristic under Static and Dynamic Conditions, Technology Scaling, power consumption. (Chapter - 1) UNIT II COMBINATIONAL LOGIC CIRCUITS Propagation Delays, stick diagram, Layout diagrams, Examples of combinational logic design, Elmore’s constant, Static Logic Gates, Dynamic Logic Gates, Pass Transistor Logic, Power Dissipation, Low Power Design principles. (Chapter - 2) UNIT III SEQUENTIAL LOGIC CIRCUITS AND CLOCKING STRATEGIES Static Latches and Registers, Dynamic Latches and Registers, Pipelines, Nonbistable Sequential Circuits. Timing classification of Digital Systems, Synchronous Design, Self-Timed Circuit Design. (Chapter - 3) UNIT IV INTERCONNECT, MEMORY ARCHITECTURE AND ARITHMETIC CIRCUITS Interconnect Parameters - Capacitance, Resistance, and Inductance, Electrical WireModels, Sequential digital circuits : adders, multipliers, comparators, shift registers. Logic Implementation using Programmable Devices (ROM, PLA, FPGA), Memory Architecture and Building Blocks, Memory Core and Memory Peripherals Circuitry. (Chapter - 4) UNIT V ASIC DESIGN AND TESTING Introduction to wafer to chip fabrication process flow. Microchip design process & issues in test and verification of complex chips, embedded cores and SOCs, Fault models, Test coding. ASIC Design Flow, Introduction to ASICs, Introduction to test benches, Writing testbenches in Verilog HDL, Automatic test pattern generation, Design for testability, Scan design : Test interface and boundary scan. (Chapter - 5)

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Pages: 384 Edition: 2023 Vendors: Technical Publications