# Digital Electronics & Logic Design for SPPU 19 Course (SE - III - Comp.- 210245) (Decode)

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Syllabus Digital Electronics and Logic Design - (210245) Credit Scheme Examination Scheme and Marks 03 Mid_Semester (TH) : 30 Marks End_Semester (TH) : 70 Marks Unit I Minimization Technique Logic Design Minimization Technique : Minimization of Boolean function using K-map (up to 4 variables) and Quine Mc-Clusky Method, Representation of signed number- sign magnitude representation ,1’s complement and 2’s complement form (red marked can be removed), Sum of product and Product of sum form, Minimization of SOP and POS using K-map. (Chapters - 1, 2) Unit II Combinational Logic Design Code converter : BCD, Excess-3, Gray code, Binary Code. Half- Adder, Full Adder, Half Subtractor, Full Subtractor, Binary Adder (IC 7483), BCD adder, Look ahead carry generator, Multiplexers (MUX): MUX (IC 74153, 74151), Cascading multiplexers, Demultiplexers (DEMUX)- Decoder (IC 74138, IC 74154), Implementation of SOP and POS using MUX, DMUX, Comparators (2 bit), Parity generators and Checker. (Chapter - 3 ) Unit III Sequential Logic Design Flip-Flop : SR, JK,D,T, Preset and Clear, Master Slave JK Flip Flops, Truth Tables and Excitation tables, Conversion from one type to another type of Flop-Flop. Registers : SISO, SIPO, PISO, PIPO, Shift Registers, Bidirectional Shift Register, Ring Counter, Universal Shift Register Counters : Asynchronous Counter, Synchronous Counter, BCD Counter, Johnson Counter, Modulus of the counter (IC 7490),Synchronous Sequential Circuit Design : Models- Moore and Mealy, State diagram and State Table ,Design Procedure, Sequence Generator and detector. (Chapters - 4, 5, 6, 7) Unit IV Algorithmic State Machines and Programmable Logic Devices Algorithmic State Machines : Finite State Machines (FSM) and ASM, ASM charts, notations, construction of ASM chart and realization for sequential circuits. PLDS : PLD, ROM as PLD, Programmable Logic Array (PLA), Programmable Array Logic (PAL), Designing combinational circuits using PLDs. (Chapters - 8, 9) Unit V Logic Families Classification of logic families : Unipolar and Bipolar Logic Families, Characteristics of Digital ICs : Fan-in, Fan-out, Current and voltage parameters, Noise immunity, Propagation Delay, Power Dissipation, Figure of Merits, Operating Temperature Range, power supply requirements. Transistor - Transistor Logic : Operation of TTL NAND Gate (Two input), TTL with active pull up, TTL with open collector output, Wired AND Connection, Tristate TTL Devices, TTL characteristics. CMOS : CMOS Inverter, CMOS characteristics, CMOS configurations- Wired Logic, Open drain outputs. (Chapter - 10) Unit VI Introduction to Computer Architecture Introduction to Ideal Microprocessor - Data Bus, Address Bus, Control Bus. Microprocessor based Systems - Basic Operation, Microprocessor operation, Block Diagram of Microprocessor. Functional Units of Microprocessor - ALU using IC 74181, Basic Arithmetic operations using ALU IC 74181, 4-bit Multiplier circuit using ALU and shift registers. Memory Organization and Operations, digital circuit using decoder and registers for memory operations. (Chapter - 11)

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