Digital Circuits for SPPU 19 Course (SE - III - E&Tc - 204182) (Decode)

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Syllabus Digital Circuits - (204182) Credit Examination Scheme : 03 In Sem(Theory): 30 Marks End Sem(Theory): 70 Marks Unit I : Digital Logic Families Classification and Characteristics of digital Logic Families : Speed, power dissipation, figure of merit, fan in, fan out, current, voltage, noise immunity, operating temperatures and power supply requirements. TTL logic. Operation of TTL NAND gate, active pull up, wired AND, open collector output, unconnected inputs. Tri-State logic. CMOS logic: CMOS inverter, NAND, NOR gates, unconnected inputs, wired logic, open drain output. Interfacing CMOS and TTL, Data sheet specifications. (Chapter - 1) Unit II : Combinational Logic Design Definition of combinational logic, canonical forms, Standard representations for logic functions, k-map representation of logic functions (SOP and POS forms), minimization of logical functions for min-terms and max-terms (upto 4 variables), don’t care conditions, Design Examples: Arithmetic Circuits, BCD to 7 segment decoder, Code converters. Introduction to Quine- McCluskey method, QuineMcCluskey using don’t care terms, Reduced prime implicants Tables. (Chapter - 2) Unit III : Combinational Circuits Adders and their use as subtractor, look ahead carry, ALU, Digital Comparator, Parity generators/checkers, Multiplexers and their use in combinational logic designs, multiplexer trees, De-multiplexers and their use in combinational logic designs, Decoders, Demultiplexer trees. (Chapter - 3) Unit IV : Sequential Logic Design 1 Bit Memory Cell, Clocked SR, JK, MS J-K flip flop, D and T flip-flops. Use of preset and clear terminals, hold and setup time and metastability. Excitation Table for flip flop, Conversion of flip flops, Typical data sheet specifications of Flip flop application of Flip flops. Registers, Shift registers, Counters (ring counters, twisted ring counters), ripple counters, Mod-n counters, up/down counters, synchronous counters, lock out, Clock Skew, Clock jitter. Effect on synchronous designs, Sequence Generators.(Chapters - 4, 5, 6) Unit V : State Machines Basic design steps - State diagram, State table, State reduction, State assignment, Mealy and Moore machines representation, Implementation, finite state machine implementation, Sequence detector. Introduction to Algorithmic state machines- construction of ASM chart and realization for sequential circuits.(Chapters - 7, 8) Unit VI : Programmable Logic Devices Programmable logic devices : Detail architecture, Study of PROM, PAL, PLA, General Architecture, features and typical specifications of FPGA and CPLD. Semiconductor memories: memory organization and operation, expanding memory size, Classification and characteristics of memories, RAM ROM, EPROM, EEPROM, NVRAM, SRAM, and DRAM. Designing combinational circuits using PLDs.(Chapters - 9, 10)

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Pages: 240 Edition: 2023 Vendors: Technical Publications