This book begins with an introduction to Verilog HDL. It describes basic concepts in Verilog HDL, language constructs and conventions and modeling styles - gate-level modeling, data-flow level modeling, behavioral modeling and switch level modeling. It also describes sequential models, basic memory components, functional register, static machine coding and sequential synthesis. The last section of the book focuses on component testing and verification. It includes combinational circuits testing, sequential circuit testing, test bench techniques, design verification and assertion verification.