Unit I : HDL Design Design flow, Language constructs, Data objects, Data types, Entity, Architecture and types of modeling, Sequential statements, Concurrent statements, Packages, Sub programs, Attributes, HDL modeling of combinational, Sequential circuits and FSM, Simulations, Synthesis, Efficient coding styles, Hierarchical and flat designs, Partitioning for synthesis, Pipelining, Resource sharing. (Chapter - 1) Unit II : Digital Design and Issues Sequential synchrnous machine design, Moore and mealy machines, HDL, code for machines, FIFO, Metastability and solutions, Noise margin, Fan-out, Skew, Timing considerations. Hazards, Clock distribution, Clock jitter, Supply and ground bounce, Power distribution techniques, Power optimization, Interconnect routing techniques; Wire parasitic, Signal integrity issues. I/O architecture. (Chapter - 2) Unit III : PLD Architectures and Applications Design flow, CPLD architecture, Features, Specifications, Applications, FPGA architecture, Features, Specifications, Applications, The simulation and synthesis tools, FPGA synthesis and implementation. (Chapter - 3) Unit IV : Digital CMOS Circuits N-MOS, P-MOS and CMOS, MOSFET parasitic, Technology scaling, Channel length modulation, Hot electron effect, Velocity saturation, CMOS inverter, Device sizing, CMOS combinational logic design, Power dissipations, Power delay product, Body effect, Rise and fall times, Latch up effect, Transmission gates. (Chapter - 4) Unit V : Application Specific Integrated Circuit Design Flow, Cell design specifications, Spice simulation, AC and DC analysis, Transfer characteristics, Transient responses, Noise analysis, Lambda rules, Design rule check, Fabrication methods of circuit elements, Layout of cell, Library cell designing for NAND and NOR, Circuit extraction, Electrical rule check, Layout Vs. schematic, Post-layout simulation and parasitic extraction, Design issues like antenna effect, Electro migration effect, Cross talk and drain punch through, Timing analysis. (Chapter - 5) Unit VI : VLSI Testing and Analysis Types of fault, Need of design for testability (DFT), DFT guideline, Testability, Fault models, Path sensitizing, Test pattern generation, Sequential circuit test, Built-in self test, JTAG and boundary scan, TAP controller. (Chapter - 6)
