Computer Organization & Architecture for GTU 18 Course (IV- CSE/IT -3140707) (Decode)

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1. Computer Data Representation Basic computer data types. Comp!ements, fixed point representation. Reqister Transfer and Micro-operations : f!oatins;ι point representation, Res;ιister Transfer Ians;ιuas;ιe, Res;ιister Transfer, Bus and Memory Transfers (Tree-State Bus Buffers. Memory Transfer). Arithmetic Micro-Operations, Los;ιic Micro-Operations, Shift Micro-Operations, Arithmetic Ios;ιica! shift uηίι (Chapters - 1, 2) 2. Basic Computer Organization and Design Instruction codes, Computer reqisters. computer instructions, Timins;ι and Contro[. Instruction cyc!e, Memory-Reference Instructions, Input-output and interrupt, Comp!ete computer description, Desis;ιn of Basic computer, Desis;ιn of Accumu!ator Unit. (Chapter - 3) 3. Assembly Language Programming Introduction, Machine Lans;ιuas;ιe, Assemb!y Lans;ιuas;ιe Pros;ιrammins;ι, Arithmetic and !oqic operations, Ioopins;ι constructs, Subroutines, 1-0 Pros;ιrammins;ι. (Chapter - 4) 4. Microprogrammed Control Organization Contro! Memory, Address sequencins;ι, Micro pros;ιram examp!e, Desis;ιn of Contro! Unit. (Chapter - 5) 5. Central Processing Unit Introduction, Genera! Reqister Ors;ιanization, Stacl.! Ors;ιanization, Instruction format, Addressins;ι Modes, Data transfer and manipu!ation, Pros;ιram control. Reduced Instruction Set Computer (RISC) & Comp!ex Instruction Set Computer (CISC). (Chapter - 6) 6. Pipeline and Vector Processing f!ynn's taxonomy, Para!Ie[ Processins;ι, Pipe!inins;ι, Arithmetic Pipe!ine, Instruction, Pipe!ine, RISC Pipe!ine, v'ector Processins;ι, Array Processors. (Chapter - 7) 7. Computer Arithmetic Introduction, Addition and subtraction, Mu!tip!ication Als;ιorithms (Booth Mu!tip!ication A!s;ιorithm), Division A!s;ιorithms, f!oatins;ι Point Arithmetic operations, Decima! Arithmetic Unit. (Chapter - 8) 8. Input-Output Organization lnput-Output Interface. Asynchronous Data Transfer. Modes Of Transfer, Priority Interrupt. DMA. Input-Output Processor (ΙΟΡ). CPUIOP Communication. Serial communication. (Chapter - 9) 9. Memory Organization Memory Hierarchy. Main Memory. Auxi!iary Memory, Associative Memory, Cache Memory, Virtua! Memory. (Chapter - 10) 10. Multiprocessors .Characteristics of Multiprocessors. Interconnection Structures. Inter-processor Arbitration. Inter-processor Communication and Synchronization, Cache Coherence, Shared Memory Mu!tiprocessors. (Chapter - 11)

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Author: [Atul P. Godse] Pages: 280 Edition: 2022 Vendors: Technical Publications