Syllabus Digital Electronics - (EE25301) Digital Fundamentals : Number Systems - Decimal, Binary, Octal, Hexadecimal, 1’s and 2’s complements, Codes - Binary, BCD, Excess 3, Gray, Alphanumeric codes, Boolean theorems, Logic gates, Universal gates, Sum of products and product of sums, Min terms and Max terms, Karnaugh map Minimization and QuineMcCluskey method of minimization. (Chapters - 1, 2) Combinational Logic Design : Design of Half and Full Adders, Half and Full Subtractors, Binary Parallel Adder - Carry look ahead Adder, BCD Adder, Binary Multiplier, Multiplexer, Demultiplexer, Magnitude Comparator, Decoder, Encoder, Priority Encoder. (Chapter - 3) Synchronous Sequential Circuits : Flip flops - SR, JK, T, D, Master/Slave. FF operation and excitation tables, Triggering of FF, Analysis and design of clocked sequential circuits - Moore/Mealy models, state minimization, state assignment, circuit implementation - Design of Counters - Ripple Counters : Binary, BCD, Modulo n, Up/Down counters - Counter for Random Sequence - Shift registers : - Universal Shift Register - Synchronous counters - Ring counter - Johnson counter. (Chapters - 4, 5, 6, 7) Asynchronous Sequential Circuits : Analysis and Design of Asynchronous Sequential Circuits-Reduction of Flow Tables - Stable and Unstable states, state reduction, output specifications, cycles and races, race free assignments, Hazards : Essential Hazards, Pulse mode sequential circuits, Design of Hazard free circuits. (Chapter - 8) Memory and Programmable Logic Devices : ROM - PROM - EPROM - EEPROM - EAPROM, RAM - Programmable Logic Devices - Programmable Logic Array (PLA) - Programmable Array Logic (PAL) - Field Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits using PLA, PAL, CPLD’s. TTL and CMOS Logic families. (Chapters - 9, 10) Hardware Description Language : Introduction to Verilog : Structure of Verilog module, Operators, data types, Styles of description - Data flow description, Implement logic gates, half adder and full adder using Verilog data flow description. Behavioral description : Structure, variable assignment statement, sequential statements, loop statements, Verilog behavioral description of Multiplexers (2 : 1, 4 : 1, 8 : 1) and De-multiplexers - Encoders (8 to 3), Decoders (2 to 4). latches-flipflops. (Chapter - 11)
