Syllabus Digital System Design - (2303113) Theory Term work Pract / Oral Total Internal Assessment End Sem Exam Exam Duration (in Hrs) Test 1 Test 2 Total 20 20 40 60 2 - - - - 100 Sr. No. Name of Module Detailed Content I. Number Systems and Codes Review of Binary, Octal and Hexadecimal Number Systems, their inter-conversion, Gray code and BCD code, Binary Addition, Subtraction using 1’s and 2’s Complement method. (Chapter - 1) II. Logic families and Minimization Techniques Classification of logic families : Unipolar and Bipolar Logic Families, Characteristics of Digital ICs, TTL and CMOS comparison. Digital logic gates, Universal gates, Realization using NAND and NOR gates, Boolean Algebra, De Morgan’s Theorem. Minimization of Boolean expressions :- SOP, POS, and Karnaugh map (up to 4 variables). (Chapter - 2) III. Combinational Logic Circuits Adder, Subtractor, Multiplexer, De-multiplexer, Code Converter, BCD adder, Magnitude Comparator, Parallel Adder, Implementation of Logic expressions using Multiplexers, De-multiplexers, Encoders and Decoders. (Chapter - 3) IV. Sequential Logic Circuits Flip flops (FF) : SR, JK, T, D, Master Slave JK flip flops, Truth table, excitation table, triggering methods, and flip flop conversions. Counters : Asynchronous and Synchronous - MOD N, UP/DOWN, Decade counter, Frequency division, Finite State Machine: Introduction to Moore and Mealy machines - Block diagram, state diagram, state tables. (Chapters - 4, 5, 6) V. Shift Registers and Programmable Logic Devices Registers : SISO, SIPO, PISO, PIPO, Universal Shift registers, Ring counter, Johnson counter, Sequence generator. Structure of Programmable Logic Devices (PLDs), Function implementation with Programmable Logic Array (PLA) and Programmable Array Logic (PAL). Introduction to CPLD and FPGA. (Chapters - 7, 8) VI. Introduction to VHDL VLSI Design flow (Frontend) : Design entry : Schematic different modeling styles in VHDL, Data types and objects, Synthesis and Simulation, implementation of combinational and sequential logic using VHDL. (Chapter - 9)
