{"product_id":"9789365219487-2","title":"Digital Principles and Computer Organization for BE Anna University R25 CBCS (II - CSE\/AI\u0026DS\/CSE(Cyber Sec.)\/CSE(AI\u0026ML) - CS25C06)","description":"\u003cp\u003eSyllabus Digital Principles and Computer Organization  - (CS25C06) Digital Logic :  Digital Systems, Integer Arithmetic, Addition and Subtraction of Signed Numbers, Boolean Algebra, Theorems and Postulates, Functions, Truth Table, Canonical and Standard Forms, Simplification using K-Maps, Digital Logic Gates, Universal gates, Implementation of Logic Gates, Integrated Circuits. (Chapters - 1, 2) Activities : •\tAssignment on Karnaugh Map. •\tBuild logic circuits. •\tVirtual demonstration of logical gates. Computer System :  Basic structure of a computer, Classes of Computer, Functional units - Interconnection of components, Von Neumann architecture and Harvard architecture - Instruction execution cycle, Performance metrics: MIPS, MFLOPS, CPI, throughput. (Chapter - 3) Activities : •\tMIPS, MFLOPS, and CPI calculations. •\tPreparations of report on comparison of two CPU from different manufacturing. Arithmetic and Logic Unit :  Combinational Circuits : Adders, Binary Adder, Binary Parallel Adder, Subtractor, Multiplexers, Decoders, Design of Fast Adder, Multiplication of Signed and Unsigned Numbers, Fast Multiplication - Integer Division, Floating Point Numbers and Operations, Booth’s algorithm for signed multiplication, Sequential Circuits : Flip-Flops, Registers, Counters. (Chapters - 4, 5, 6, 7) Activities : •\tVirtual demonstration on Binary adder. •\tBuild a parallel order. Processing and Pipelining :  Instruction Set Architecture : RISC vs CISC, Addressing modes, Hardwired control and Micro programmed control unit, Concepts of Pipelining, Pipeline stages and Timing diagram, Hazards : Structural, Data and Control Hazards, Instruction-level parallelism, Parallel processing concepts : SIMD, MIMD, Superscalar processors, Vector and Array Processor. (Chapters - 8, 9, 10) Activities : •\tComparison of RISC-V and x86 ISAs; present findings on their relevance to AI accelerators. •\tSpot and resolve different types of pipeline hazards in given scenarios. Memory  :  Memory hierarchy : Registers, Cache, Main Memory- RAM- ROM : PROM, EPROM, EEPROM-Secondary storage, HDD, SSD, Cache Organization, Cache replacement policies, NUMA- DMA- ECC. (Chapter - 11) I\/O Systems  I\/O Techniques : Programmed, Interrupt-Driven, DMA, I\/O Devices and Interface  Standards : PCI, USB, SATA, Interrupt Types and Priority Handling, Buses and Bus Arbitration, Peripheral Communication. (Chapter - 12) Activities : •\tVirtual demonstration of DMA. •\tI\/O in Real AI Systems.\u003c\/p\u003e","brand":"Technical Publications","offers":[{"title":"Default Title","offer_id":47343697330347,"sku":"12446062895","price":795.0,"currency_code":"INR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0620\/3355\/9723\/files\/WhatsApp_Image_2025-11-22_at_10.47.28_1_c4aca81b-876b-4eab-8aa2-6cfa9a0d7c32.jpg?v=1783178201","url":"https:\/\/technicalpublications.in\/products\/9789365219487-2","provider":"Technical Publications","version":"1.0","type":"link"}