VLSI Design and Technology for SPPU 19 Course (BE - SEM VII - E&Tc 404182)

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Unit I : Design with HDL Design Flow, Language constructs, Data objects, Data types, Entity, Architecture & types of modeling, Sequential statements, Concurrent statements, Packages, Sub programs, Attributes, HDL modeling of Combinational, Sequential circuits and FSM. Simulations, Synthesis, Efficient coding styles, Hierarchical and flat designs, Partitioning for synthesis, Pipelining, Resource sharing. (Chapter - 1) Unit II : Digital Design and Issues Sequential synchronous machine design, Moore and Mealy machines, HDL code for Machines, FIFO. Meta-stability and solutions. Noise margin, Fan-out, Skew, Timing considerations, Hazards, Clock distribution, Clock jitter, Supply and ground bounce, Power distribution techniques, Power optimization. Interconnect routing techniques, Wire parasitic, Signal integrity issues. I/O architecture. (Chapter - 2) Unit III : PLD Architectures and Applications Design Flow. CPLD Architecture, Features, Specifications, Applications. FPGA Architecture, Features, Specifications, Applications. Clock management techniques. The Simulation and Synthesis Tools, FPGA synthesis and implementation. Comparison of CPLD & FPGA. (Chapter - 3) Unit IV : Digital CMOS Circuits N-MOS, P-MOS and CMOS. MOSFET parasitic, Technology scaling, Channel length modulation, Hot electron effect, Velocity saturation. CMOS Inverter, Device sizing, CMOS combinational logic design, Power dissipations, Power delay product, Body Effect, Rise and fall times, Latch Up effect, Transmission gates. (Chapter - 4) Unit V : Application Specific Integrated Circuits Design Flow, Cell design specifications, Spice simulation, AC and DC analysis, Transfer Characteristics, Transient responses, Noise analysis, Lambda rules, Design Rule Check, Fabrication methods of circuit elements, Layout of cell, Library cell designing for NAND & NOR, Circuit Extraction, Electrical Rule Check, Layout Vs. Schematic, Post-layout Simulation and Parasitic extraction, Design Issues like Antenna effect, Electro migration effect, Cross talk and Drain punch through, Timing analysis. (Chapter - 5) Unit VI : VLSI Testing and Analysis Types of fault, Need of Design for Testability (DFT), DFT Guideline, Testability, Fault models, Path sensitizing, Test pattern generation, Sequential circuit test, Built In Self Test, JTAG & Boundary scan, TAP Controller. (Chapter - 6)

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Author: [V.S. Bagad, Rana S. Mahajan] Pages: 256 Edition: 2022 Vendors: Technical Publications